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? semiconductor components industries, llc, 2012 november, 2012 ? rev. 1 1 publication order number: amis ? 30543/d amis-30543 micro-stepping motor driver introduction the amis ? 30543 is a micro ? stepping stepper motor driver for bipolar stepper motors. the chip is connected through i/o pins and an spi interface with an external microcontroller. it has an on ? chip voltage regulator, reset ? output and watchdog reset, able to supply peripheral devices. amis ? 30543 contains a current ? translation table and takes the next micro ? step depending on the clock signal on the ?nxt? input pin and the status of the ?dir? (=direction) register or input pin. the chip provides a so ? called ?speed and load angle? output. this allows the creation of stall detection algorithms and control loops based on load ? angle to adjust torque and speed. it is using a proprietary pwm algorithm for reliable current control. the amis ? 30543 is implemented in i2t100 technology, enabling both high ? voltage analog circuitry and digital functionality on the same chip. the chip is fully compatible with the automotive voltage requirements. the amis ? 30543 is ideally suited for general ? purpose stepper motor applications in the automotive, industrial, medical, and marine environment. w ith the on ? chip voltage regulator it further reduces the bom for mechatronic stepper applications. key features ? dual h ? bridge for 2 ? phase stepper motors ? programmable peak ? current up to 3 a ? on ? chip current translator ? spi interface ? speed and load angle output ? eleven step modes from full step up to 128 micro ? steps ? fully integrated current ? sense ? pwm current control with automatic selection of fast and slow decay ? low emc pwm with selectable voltage slopes ? active fly ? back diodes ? full output protection and diagnosis ? thermal warning and shutdown ? compatible with 5 v and 3.3 v microcontrollers ? integrated 5 v regulator to supply external microcontroller ? integrated reset function to reset external microcontroller ? integrated watchdog function ? these devices are pb ? free and are rohs compliant see detailed ordering and shipping information in the package dimensions section on page 37 of this data sheet. ordering information http://onsemi.com marking diagram qfn32 case 485j 132 32 amis30543 0c543 ? 001 awlyywwg 1 a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free package
amis ? 30543 http://onsemi.com 2 block diagram temp . sense spi otp timebase por di do cs clk nxt sla dir err band ? gap load angle amis ? 30543 logic & registers chargepump t r a n s l a t o r vreg clr vbb p w m i ? sense emc p w m i ? sense emc vdd gnd motxp motxn motyp motyn cpn cpp vcp por/wd tst0 figure 1. block diagram amis ? 30543 1 2 3 5 4 6 7 8 24 23 22 20 21 19 18 17 9 10111213141516 32 31 30 29 28 27 26 25 do di cpn motxp gnd gnd motxp motyn por/wd motyp clk vdd clr cs dir nxt sla amis ? 30543 gnd gnd gnd motyn motxn motxn motyp vbb tsto cpp vcp vbb err figure 2. pin out amis ? 30543
amis ? 30543 http://onsemi.com 3 table 1. pin list and description name pin description type equivalent schematic gnd 1 ground supply di 2 spi data in digital input type 2 clk 3 spi clock input digital input type 2 nxt 4 next micro ? step input digital input type 2 dir 5 direction input digital input type 2 err 6 error output (open drain) digital output type 4 sla 7 speed load angle output analog output type 5 / 8 no function (to be left open in normal operation) cpn 9 negative connection of charge pump capacitor high voltage cpp 10 positive connection of charge pump capacitor high voltage vcp 11 charge pump filter ? capacitor high voltage clr 12 ?clear? = chip reset input digital input type 1 cs 13 spi chip select input digital input type 2 vbb 14 high voltage supply input supply type 3 motyp 15, 16 negative end of phase y coil output driver output gnd 17, 18 ground, heat sink supply motyn 19, 20 positive end of phase y coil output driver output motxn 21, 22 positive end of phase x coil output driver output gnd 23, 24 ground, heat sink supply motxp 25, 26 negative end of phase x coil output driver output vbb 27 high voltage supply input supply type 3 por /wd 28 power ? on ? reset and watchdog reset output (open drain) digital output type 4 tst0 29 test pin input (to be tied to ground in normal operation) digital input / 30 no function (to be left open in normal operation) do 31 spi data output (open drain) digital output type 4 vdd 32 logic supply output (needs external decoupling capacitor) supply type 3 table 2. absolute maximum ratings symbol parameter min max unit v bb analog dc supply voltage (note 1) ? 0.3 +40 v t st storage temperature ? 55 +160 c t j junction temperature under bias (note 2) ? 50 +175 c v esd electrostatic discharges on component level, all pins (note 3) ? 2 +2 kv v esd electrostatic discharges on component level, hiv pins (note 4) ? 8 +8 kv stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. for limited time < 0.5 s. 2. circuit functionality not guaranteed. 3. human body model (100 pf via 1.5 k , according to jedec eia ? jesd22 ? a114 ? b). 4. hiv = high voltage pins motxx, v bb , gnd; (100 pf via 1.5 k , according to jedec eia ? jesd22 ? a114 ? b).
amis ? 30543 http://onsemi.com 4 equivalent schematics following figure gives the equivalent schematics of the user relevant inputs and outputs. the diagrams are simplified representations of the circuits used. in rin 4k in 4k type 1: clr input type 2 : clk , di, csb , nxt , dir inputs . vdd vdd type 3: vdd and vbb power supply inputs vbb vbb out type 4: do, errb and porb/wd open drain outputs sla rout type 5: sla analog output figure 3. in ? and output equivalent diagrams
amis ? 30543 http://onsemi.com 5 package thermal characteristics the amis ? 30543 is available in a nqfp32 package. for cooling optimizations, the nqfp has an exposed thermal pad which has to be soldered to the pcb ground plane. the ground plane needs thermal vias to conduct the heat to the bottom layer. figure 4 gives an example for good power distribution solutions. for precise thermal cooling calculations the major thermal resistances of the device are given in table 5. the thermal media to which the power of the devices has to be given are: ? static environmental air (via the case) ? pcb board copper area (via the exposed pad) the major thermal resistances of the device are the rth from the junction to the ambient (rthja) and the overall rth from the junction to exposed pad (rthjp). in table 4 below one can find the values for the rthja and rthjp, simulated according to jesd ? 51. the rthja for 2s2p is simulated conform jedec jesd ? 51 as follows: ? a 4 ? layer printed circuit board with inner power planes and outer (top and bottom) signal layers is used ? board thickness is 1.46 mm (fr4 pcb material) ? the 2 signal layers: 70 m thick copper with an area of 5500 mm 2 copper and 20% conductivity ? the 2 power internal planes: 36 m thick copper with an area of 5500 mm 2 copper and 90% conductivity the rthja for 1s0p is simulated conform to jedec jesd ? 51 as follows: ? a 1 ? layer printed circuit board with only 1 layer ? board thickness is 1.46 mm (fr4 pcb material) ? the layer has a thickness of 70 m copper with an area of 5500 mm 2 copper and 20% conductivity ??????????????????? ??????????????????? ??????????????????? ??????????????????? ??????????????????? ??????????????????? ??????????????????? ??????????????????? ??????????????????? nqfp ? 32 figure 4. example of nqfp ? 32 pcb ground plane layout in top view (preferred layout at top and bottom) electrical specification recommend operation conditions operating ranges define the limits for functional operation and parametric characteristics of the device. note that the functionality of the chip outside these operating ranges is not guaranteed. operating outside the recommended operating ranges for extended periods of time may affect device reliability. table 3. operating ranges symbol parameter min max unit v bb analog dc supply +6 +30 v t j junction temperature (note 5) ? 40 +172 c 5. no more than 100 cumulative hours in life time above t tw .
amis ? 30543 http://onsemi.com 6 table 4. dc parameters (the dc parameters are given for v bb and temperature in their operating ranges unless otherwise specified) convention: currents flowing in the circuit are defined as positive. symbol pin(s) parameter remark/test conditions min typ max unit supply and voltage regulators v bb v bb nominal operating supply range 6 30 v i bb total internal current consumption (note 6) unloaded outputs 12 ma v dd v dd regulated output voltage i load within limits 4.5 5 5.5 v v dd_slp regulated output voltage in sleep mode ? 1 ma i load 0 ma v bb > 9 v 4 5.5 v i int internal load current (note 6) unloaded outputs 8 ma i load max output current 6 v v bb < 8 v 15 8 v v bb 30 v 40 i ddlim current limitation pin shorted to ground 200 ma i load_slp current consumption when in sleep mode v bb > 9 v 230 a power ? on ? reset (por) v ddh v dd internal por comparator threshold v dd rising 3.9 4.2 4.4 v v ddl internal por comparator threshold v dd falling 3.86 v v ddhys internal por comparator hysteresis 0.35 v motordriver i mdmax,peak motxp motxn motyp motyn max current through motor coil in normal operation t j = 130 c 3000 ma r hs on ? resistance high ? side driver, cur[4:0] = 0...31 (note 7) 0.15 0.4 t j = 160 c 0.45 r ls3 on ? resistance low ? side driver, cur[4:0] = 16...25 (note 7) 0.1 0.4 t j = 160 c 0.45 r ls2 on ? resistance low ? side driver, cur[4:0] = 10...15 (note 7) 0.2 0.7 t j = 160 c 0.8 r ls1 on ? resistance low ? side driver, cur[4:0] = 3...9 (note 7) 0.4 1.1 t j = 160 c 1.25 r ls0 on ? resistance low ? side driver, cur[4:0] = 0...2 (note 7) 0.8 2.2 t j = 160 c 2.50 digital inputs i leak di, clk nxt, dir clr, cs input leakage (note 8) t j = 160 c 1 a v il logic low threshold 0 0.65 v v ih logic high threshold 2.35 v dd v r pd_clr clr internal pulldown resistor 120 200 300 k r pd_tst tst0 internal pulldown resistor 3 9 k 6. current with oscillator running, all analogue cells active, spi communication and nxt pulses applied. no floating inputs. par ameter guaranteed by design. 7. characterization data only 8. not valid for pins with internal pulldown resistor
amis ? 30543 http://onsemi.com 7 table 4. dc parameters (the dc parameters are given for v bb and temperature in their operating ranges unless otherwise specified) convention: currents flowing in the circuit are defined as positive. symbol unit max typ min remark/test conditions parameter pin(s) digital outputs v ol do, err , por /wd logic low level open drain i ol = 5 ma 0.5 v thermal warning and shutdown t tw thermal warning 150 160 170 c t tsd thermal shutdown (notes 9 and 10) t tw + 20 c charge pump v cp vcp output voltage 6 v< v bb < 15 v 2 * v bb ? 2 v 15 v < v bb < 30 v v bb + 9 v bb + 12.5 v bb +16 v c buffer external buffer capacitor 180 220 470 nf c pump cpp cpn external pump capacitor 180 220 470 nf package thermal resistance value rth ja nqfp thermal resistance junction ? to ? ambient simulated conform jedec jesd ? 51, 2s2p 30 k/w simulated conform jedec jesd ? 51, 1s0p 60 k/w rth jp nqfp thermal resistance junction ? to ? exposed pad 0.95 k/w speed and load angle output v out sla output voltage range 0.2 v dd ? 0.2 v v off output offset sla pin ? 50 50 mv g sla gain of sla pin = v bemf / v coil slag = 0 0.5 slag = 1 0.25 r out output resistance sla pin 1 k 9. no more than 100 cumulated hours in life time above t tw . 10. thermal shutdown is derived from thermal warning. characterization data only.
amis ? 30543 http://onsemi.com 8 table 5. ac parameters (the ac parameters are given for v bb and temperature in their operating ranges) symbol pin(s) parameter remark/test conditions min typ max unit internal oscillator f osc frequency of internal oscillator 3.6 4 4.4 mhz motor driver f pwm motxx pwm frequency frequency depends only on internal oscillator 20.5 22.8 25.1 khz double pwm frequency 41.0 45.6 50.2 khz tb rise motxx turn ? on voltage slope, 10% to 90% emc[1:0] = 00 200 v/ s emc[1:0] = 01 140 v/ s emc[1:0] = 10 70 v/ s emc[1:0] = 11 35 v/ s tb fall motxx turn ? off voltage slope, 90% to 10% emc[1:0] = 00 200 v/ s emc[1:0] = 01 140 v/ s emc[1:0] = 10 70 v/ s emc[1:0] = 11 35 v/ s digital outputs t h2l do err output fall ? time from v inh to v inl capacitive load 400 pf and pullup resistor of 1.5 k 50 ns charge pump f cp cpn cpp charge pump frequency 250 khz t cpu motxx startup time of charge pump (note 11) spec external components 5 ms clr function t clr clr hard reset duration time 100 s power ? up t pu por /wd powerup time v bb = 12 v, i load = 50 ma, c load = 220 nf 100 s t por reset duration see figure 16 100 ms t rf reset filter time see figure 16 0.5 s watchdog t wdto por /wd watchdog time out interval 32 512 ms t wdpr prohibited watchdog acknowledge delay 2 ms nxt function t nxt_hi nxt nxt minimum, high pulse width see figure 5 2 s t nxt_hi nxt minimum, low pulse width see figure 5 2 s t dir_set nxt hold time, following change of dir see figure 5 0.5 s t dir_hold nxt hold time, before change of dir see figure 5 0.5 s 11. guaranteed by design
amis ? 30543 http://onsemi.com 9 dir nxt valid t nxt_hi t nxt_lo t dir_set t dir_hold 0.5 v cc figure 5. nxt ? input timing diagram table 6. spi timing parameters symbol parameter min typ max unit t clk spi clock period 1 s t clk_high spi clock high time 100 ns t clk_low spi clock low time 100 ns t set_di di set up time, valid data before rising edge of clk 50 ns t hold_di di hold time, hold data after rising edge of clk 50 ns t csb_high cs high time 2.5 s t set_csb cs set up time, cs low before rising edge of clk 100 ns t set_clk clk set up time, clk low before rising edge of cs 100 ns figure 6. spi timing
amis ? 30543 http://onsemi.com 10 typical application schematic por/wd vcp cpp cpn clr c 7 err gnd cs clk di do nxt dir motxp motxn motyp motyn m 220 nf 100 nf c 5 v bat vdd vbb vbb 100 nf 220 nf 100 f c 2 c 3 c 6 c 1 100 nf 100 nf c 4 sla c 8 r 1 c d 1 r 2 r 3 r 4 amis ? 30543 2 15, 16 12 10 11 23 5 4 1 21, 22 18 3 17 19, 20 7 9 13 28 6 14 24 25, 26 27 tsto 29 31 32 figure 7. typical application schematic amis ? 30543 table 7. external components list and description component function typ value tolerance unit c 1 v bb buffer capacitor (note 12) 100 ? 20 +80% f c 2 , c 3 v bb decoupling block capacitor (note 13) 100 ? 20 +80% nf c 4 v dd buffer capacitor 100 20% nf c 5 v dd buffer capacitor 100 20% nf c 6 charge pump buffer capacitor 220 20% nf c 7 charge pump pumping capacitor 220 20% nf c 8 low pass filter sla 1 20% nf r 1 low pass filter sla 5.6 1% k r 2, r 3, r 4 pullup resistor open drain output 4.7 1% k d 1 optional reverse protection diode murd530 12. esr < 1 . 13. esr < 50 m .
amis ? 30543 http://onsemi.com 11 functional description h ? bridge drivers a full h ? bridge is integrated for each of the two stator windings. each h ? bridge consists of two low ? side and two high ? side n ? type mosfet switches. writing logic ?0? in bit disables all drivers (high ? impedance). writing logic ?1? in this bit enables both bridges and current can flow in the motor stator windings. in order to avoid large currents through the h ? bridge switches, it is guaranteed that the top ? and bottom ? switches of the same half ? bridge are never conductive simultaneously (interlock delay). a two ? stage protection against shorts on motor lines is implemented. in a first stage, the current in the driver is limited. secondly, when excessive voltage is sensed across the transistor, the transistor is switched off. in order to reduce the radiated/conducted emission, voltage slope control is implemented in the output switches. the output slope is defined by the gate ? drain capacitance of output transistor and the (limited) current that drives the gate. there are two trimming bits for slope control (see table 12 spi control parameter overview emc[1:0]). the power transistors are equipped with so ? called ?active diodes?: when a current is forced trough the transistor switch in the reverse direction, i.e. from source to drain, then the transistor is switched on. this ensures that most of the current flows through the channel of the transistor instead of through the inherent parasitic drain ? bulk diode of the transistor. depending on the desired current range and the micro ? step position at hand, the r ds(on) of the low ? side transistors will be adapted such that excellent current ? sense accuracy is maintained. the r ds(on) of the high ? side transistors remain unchanged; see table 4 dc parameters for more details. pwm current control a pwm comparator compares continuously the actual winding current with the requested current and feeds back the information to a digital regulation loop. this loop then generates a pwm signal, which turns on/off the h ? bridge switches. the switching points of the pwm duty ? cycle are synchronized to the on ? chip pwm clock. the frequency of the pwm controller can be doubled and an artificial jitter can be added (see t able 12 spi control parameter overview pwmj). the pwm frequency will not vary with changes in the supply voltage. also variations in motor ? speed or load ? conditions of the motor have no effect. there are no external components required to adjust the pwm frequency. automatic forward and slow ? fast decay the pwm generation is in steady ? state using a combination of forward and slow ? decay. the absence of fast ? decay in this mode, guarantees the lowest possible current ? ripple ?by design?. for transients to lower current levels, fast ? decay is automatically activated to allow high ? speed response. the selection of fast or slow decay is completely transparent for the user and no additional parameters are required for operation. icoil 0 t forward & slow decay forward & slow decay fast decay & forward actual value set value t pwm figure 8. forward and slow/fast decay pwm
amis ? 30543 http://onsemi.com 12 automatic duty cycle adaptation in case the supply voltage is lower than 2*bemf, then the duty cycle of the pwm is adapted automatically to > 50% to maintain the requested average current in the coils. this process is completely automatic and requires no additional parameters for operation. the over ? all current ? ripple is divided by two if pwm frequency is doubled (see table 12 spi control parameter overview pwmf) actual value duty cycle <50% duty cycle > 50% duty cycle < 50% t icoil set value t pwm figure 9. automatic duty cycle adaption step translator and step mode the step translator provides the control of the motor by means of sm[2:0], esm[2:0], spi register dirctrl and input pins dir and nxt. it is translating consecutive steps in corresponding currents in both motor coils for a given step mode. one out of eleven possible stepping modes can be selected through spi ? bits sm[2:0] and esm[2:0] (see table 12 spi control parameter overview). after power ? on or hard reset, the coil ? current translator is set to the default 1/32 micro ? stepping at position ?0?. when remaining in the same step mode, subsequent translator positions are all in the same column and increased or decreased with 1. table 9 lists the output current vs. the translator position. as shown in figure 10 the output current ? pairs can be projected approximately on a circle in the (i x , i y ) plane. there are, however, two exceptions: uncompensated half step and uncompensated full step. in these step modes the currents are not regulated to a fraction of i max but are in all intermediate steps regulated at 100%. in the (i x , i y ) plane the current ? pairs are projected on a square. table 8 lists the output current vs. the translator position for these cases. table 8. square translator table for uncompensated full step and uncompensated half step msp[8:0] stepmode ( sm[2:0] ) % of i max 101 110 coil x coil y uncompensated half step uncompensated full step 0 0000 0000 0 ? 0 100 0 0100 0000 1 1 100 100 0 1000 0000 2 ? 100 0 0 1100 0000 3 2 100 ? 100 1 0000 0000 4 ? 0 ? 100 1 0100 0000 5 3 ? 100 ? 100 1 1000 0000 6 ? ? 100 0 1 1100 0000 7 0 ? 100 100
amis ? 30543 http://onsemi.com 13 table 9. circular translator table msp[8:0] sm[2:0] % of imax xxx xxx 000 001 010 011 100 xxx xxx esm[2:0] 001 010 000 000 000 000 000 011 100 1/128 1/64 1/32 1/16 1/8 1/4 comp 1/2 comp full 2ph comp full 1ph coil x coil y 000000000 0 0 0 0 0 0 0 0 0 100 000000001 1 1 100 000000010 2 1 2 100 000000011 3 4 100 000000100 4 2 1 5 100 000000101 5 6 100 000000110 6 3 7 100 000000111 7 9 100 000001000 8 4 2 1 10 100 000001001 9 11 99 000001010 10 5 12 99 000001011 11 13 99 000001100 12 6 3 15 99 000001101 13 16 99 000001110 14 7 17 99 000001111 15 18 98 000010000 16 8 4 2 1 20 98 000010001 17 21 98 000010010 18 9 22 98 000010011 19 23 97 000010100 20 10 5 24 97 000010101 21 25 97 000010110 22 11 27 96 000010111 23 28 96 000011000 24 12 6 3 29 96 000011001 25 30 95 000011010 26 13 31 95 000011011 27 33 95 000011100 28 14 7 34 94 000011101 29 35 94 000011110 30 15 36 93 00001 1111 31 37 93 000100000 32 16 8 4 2 1 38 92 000100001 33 39 92 000100010 34 17 41 91 000100011 35 42 91 000100100 36 18 9 43 90 000100101 37 44 90 000100110 38 19 45 89 000100111 39 46 89 000101000 40 20 10 5 47 88 000101001 41 48 88 000101010 42 21 49 87
amis ? 30543 http://onsemi.com 14 table 9. circular translator table (continued) msp[8:0] % of imax sm[2:0] msp[8:0] % of imax xxx xxx 100 011 010 001 000 xxx xxx msp[8:0] % of imax esm[2:0] msp[8:0] % of imax 100 011 000 000 000 000 000 010 001 msp[8:0] coil y coil x comp full 1ph comp full 2ph comp 1/2 1/4 1/8 1/16 1/32 1/64 1/128 000101011 43 50 86 000101100 44 22 11 51 86 000101101 45 52 85 000101110 46 23 53 84 000101111 47 55 84 000110000 48 24 12 6 3 56 83 000110001 49 57 82 000110010 50 25 58 82 000110011 51 59 81 000110100 52 26 13 60 80 000110101 53 61 80 000110110 54 27 62 79 000110111 55 62 78 000111000 56 28 14 7 63 77 000111001 57 64 77 000111010 58 29 65 76 000111011 59 66 75 000111100 60 30 15 67 74 000111101 61 68 73 0001 11110 62 31 69 72 0001 11111 63 70 72 001000000 64 32 16 8 4 2 1 0 71 71 001000001 65 72 70 001000010 66 33 72 69 001000011 67 73 68 001000100 68 34 17 74 67 001000101 69 75 66 001000110 70 35 76 65 001000111 71 77 64 001001000 72 36 18 9 77 63 001001001 73 78 62 001001010 74 37 79 62 001001011 75 80 61 001001100 76 38 19 80 60 001001101 77 81 59 001001110 78 39 82 58 001001111 79 82 57 001010000 80 40 20 10 5 83 56 001010001 81 84 55 001010010 82 41 84 53 001010011 83 85 52 001010100 84 42 21 86 51 001010101 85 86 50
amis ? 30543 http://onsemi.com 15 table 9. circular translator table (continued) msp[8:0] % of imax sm[2:0] msp[8:0] % of imax xxx xxx 100 011 010 001 000 xxx xxx msp[8:0] % of imax esm[2:0] msp[8:0] % of imax 100 011 000 000 000 000 000 010 001 msp[8:0] coil y coil x comp full 1ph comp full 2ph comp 1/2 1/4 1/8 1/16 1/32 1/64 1/128 001010110 86 43 87 49 001010111 87 88 48 001011000 88 44 22 11 88 47 001011001 89 89 46 001011010 90 45 89 45 001011011 91 90 44 001011100 92 46 23 90 43 001011101 93 91 42 001011110 94 47 91 41 00101 1111 95 92 39 001100000 96 48 24 12 6 3 92 38 001100001 97 93 37 001100010 98 49 93 36 001100011 99 94 35 001100100 100 50 25 94 34 001100101 101 95 33 001100110 102 51 95 31 001100111 103 95 30 001101000 104 52 26 13 96 29 001101001 105 96 28 001101010 106 53 96 27 001101011 107 97 25 001101100 108 54 27 97 24 001101101 109 97 23 001101110 110 55 98 22 001101111 111 98 21 001110000 112 56 28 14 7 98 20 001110001 113 98 18 001110010 114 57 99 17 001110011 115 99 16 001110100 116 58 29 99 15 001110101 117 99 13 001110110 118 59 99 12 001110111 119 99 11 001111000 120 60 30 15 100 10 001111001 121 100 9 001111010 122 61 100 7 001111011 123 100 6 001111100 124 62 31 100 5 001111101 125 100 4 001111110 126 63 100 2 001111111 127 100 1 010000000 128 64 32 16 8 4 2 1 100 0
amis ? 30543 http://onsemi.com 16 table 9. circular translator table (continued) msp[8:0] % of imax sm[2:0] msp[8:0] % of imax xxx xxx 100 011 010 001 000 xxx xxx msp[8:0] % of imax esm[2:0] msp[8:0] % of imax 100 011 000 000 000 000 000 010 001 msp[8:0] coil y coil x comp full 1ph comp full 2ph comp 1/2 1/4 1/8 1/16 1/32 1/64 1/128 010000001 129 100 ? 1 010000010 130 65 100 ? 2 010000011 131 100 ? 4 010000100 132 66 33 100 ? 5 010000101 133 100 ? 6 010000110 134 67 100 ? 7 010000111 135 100 ? 9 010001000 136 68 34 17 100 ? 10 010001001 137 99 ? 11 010001010 138 69 99 ? 12 010001011 139 99 ? 13 010001100 140 70 35 99 ? 15 010001101 141 99 ? 16 010001110 142 71 99 ? 17 010001111 143 98 ? 18 010010000 144 72 36 18 9 98 ? 20 010010001 145 98 ? 21 010010010 146 73 98 ? 22 010010011 147 97 ? 23 010010100 148 74 37 97 ? 24 010010101 149 97 ? 25 010010110 150 75 96 ? 27 010010111 151 96 ? 28 010011000 152 76 38 19 96 ? 29 010011001 153 95 ? 30 010011010 154 77 95 ? 31 010011011 155 95 ? 33 010011100 156 78 39 94 ? 34 010011101 157 94 ? 35 010011110 158 79 93 ? 36 01001 1111 159 93 ? 37 010100000 160 80 40 20 10 5 92 ? 38 010100001 161 92 ? 39 010100010 162 81 91 ? 41 010100011 163 91 ? 42 010100100 164 82 41 90 ? 43 010100101 165 90 ? 44 010100110 166 83 89 ? 45 010100111 167 89 ? 46 010101000 168 84 42 21 88 ? 47 010101001 169 88 ? 48 010101010 170 85 87 ? 49 010101011 171 86 ? 50
amis ? 30543 http://onsemi.com 17 table 9. circular translator table (continued) msp[8:0] % of imax sm[2:0] msp[8:0] % of imax xxx xxx 100 011 010 001 000 xxx xxx msp[8:0] % of imax esm[2:0] msp[8:0] % of imax 100 011 000 000 000 000 000 010 001 msp[8:0] coil y coil x comp full 1ph comp full 2ph comp 1/2 1/4 1/8 1/16 1/32 1/64 1/128 010101100 172 86 43 86 ? 51 010101101 173 85 ? 52 010101110 174 87 84 ? 53 010101111 175 84 ? 55 010110000 176 88 44 22 11 83 ? 56 010110001 177 82 ? 57 010110010 178 89 82 ? 58 010110011 179 81 ? 59 010110100 180 90 45 80 ? 60 010110101 181 80 ? 61 010110110 182 91 79 ? 62 010110111 183 78 ? 62 010111000 184 92 46 23 77 ? 63 010111001 185 77 ? 64 010111010 186 93 76 ? 65 010111011 187 75 ? 66 010111100 188 94 47 74 ? 67 010111101 189 73 ? 68 0101 11110 190 95 72 ? 69 0101 11111 191 72 ? 70 011000000 192 96 48 24 12 6 3 1 71 ? 71 011000001 193 70 ? 72 011000010 194 97 69 ? 72 011000011 195 68 ? 73 011000100 196 98 49 67 ? 74 011000101 197 66 ? 75 011000110 198 99 65 ? 76 011000111 199 64 ? 77 011001000 200 100 50 25 63 ? 77 011001001 201 62 ? 78 011001010 202 101 62 ? 79 011001011 203 61 ? 80 011001100 204 102 51 60 ? 80 011001101 205 59 ? 81 011001110 206 103 58 ? 82 011001111 207 57 ? 82 011010000 208 104 52 26 13 56 ? 83 011010001 209 55 ? 84 011010010 210 105 53 ? 84 011010011 211 52 ? 85 011010100 212 106 53 51 ? 86 011010101 213 50 ? 86 011010110 214 107 49 ? 87
amis ? 30543 http://onsemi.com 18 table 9. circular translator table (continued) msp[8:0] % of imax sm[2:0] msp[8:0] % of imax xxx xxx 100 011 010 001 000 xxx xxx msp[8:0] % of imax esm[2:0] msp[8:0] % of imax 100 011 000 000 000 000 000 010 001 msp[8:0] coil y coil x comp full 1ph comp full 2ph comp 1/2 1/4 1/8 1/16 1/32 1/64 1/128 011010111 215 48 ? 88 011011000 216 108 54 27 47 ? 88 011011001 217 46 ? 89 011011010 218 109 45 ? 89 011011011 219 44 ? 90 011011100 220 110 55 43 ? 90 011011101 221 42 ? 91 011011110 222 111 41 ? 91 011011111 223 39 ? 92 011100000 224 112 56 28 14 7 38 ? 92 011100001 225 37 ? 93 011100010 226 113 36 ? 93 011100011 227 35 ? 94 011100100 228 114 57 34 ? 94 011100101 229 33 ? 95 011100110 230 115 31 ? 95 011100111 231 30 ? 95 011101000 232 116 58 29 29 ? 96 011101001 233 28 ? 96 011101010 234 117 27 ? 96 011101011 235 25 ? 97 011101100 236 118 59 24 ? 97 011101101 237 23 ? 97 011101110 238 119 22 ? 98 011101111 239 21 ? 98 011110000 240 120 60 30 15 20 ? 98 011110001 241 18 ? 98 011110010 242 121 17 ? 99 011110011 243 16 ? 99 011110100 244 122 61 15 ? 99 011110101 245 13 ? 99 011110110 246 123 12 ? 99 011110111 247 11 ? 99 011111000 248 124 62 31 10 ? 100 011111001 249 9 ? 100 011111010 250 125 7 ? 100 011111011 251 6 ? 100 011111100 252 126 63 5 ? 100 011111101 253 4 ? 100 011111110 254 127 2 ? 100 011111111 255 1 ? 100 100000000 256 128 64 32 16 8 4 2 0 ? 100 100000001 257 ? 1 ? 100
amis ? 30543 http://onsemi.com 19 table 9. circular translator table (continued) msp[8:0] % of imax sm[2:0] msp[8:0] % of imax xxx xxx 100 011 010 001 000 xxx xxx msp[8:0] % of imax esm[2:0] msp[8:0] % of imax 100 011 000 000 000 000 000 010 001 msp[8:0] coil y coil x comp full 1ph comp full 2ph comp 1/2 1/4 1/8 1/16 1/32 1/64 1/128 100000010 258 129 ? 2 ? 100 100000011 259 ? 4 ? 100 100000100 260 130 65 ? 5 ? 100 100000101 261 ? 6 ? 100 100000110 262 131 ? 7 ? 100 100000111 263 ? 9 ? 100 100001000 264 132 66 33 ? 10 ? 100 100001001 265 ? 11 ? 99 100001010 266 133 ? 12 ? 99 100001011 267 ? 13 ? 99 100001100 268 134 67 ? 15 ? 99 100001101 269 ? 16 ? 99 100001110 270 135 ? 17 ? 99 100001111 271 ? 18 ? 98 100010000 272 136 68 34 17 ? 20 ? 98 100010001 273 ? 21 ? 98 100010010 274 137 ? 22 ? 98 100010011 275 ? 23 ? 97 100010100 276 138 69 ? 24 ? 97 100010101 277 ? 25 ? 97 100010110 278 139 ? 27 ? 96 100010111 279 ? 28 ? 96 100011000 280 140 70 35 ? 29 ? 96 100011001 281 ? 30 ? 95 100011010 282 141 ? 31 ? 95 100011011 283 ? 33 ? 95 100011100 284 142 71 ? 34 ? 94 100011101 285 ? 35 ? 94 100011110 286 143 ? 36 ? 93 10001 1111 287 ? 37 ? 93 100100000 288 144 72 36 18 9 ? 38 ? 92 100100001 289 ? 39 ? 92 100100010 290 145 ? 41 ? 91 100100011 291 ? 42 ? 91 100100100 292 146 73 ? 43 ? 90 100100101 293 ? 44 ? 90 100100110 294 147 ? 45 ? 89 100100111 295 ? 46 ? 89 100101000 296 148 74 37 ? 47 ? 88 100101001 297 ? 48 ? 88 100101010 298 149 ? 49 ? 87 100101011 299 ? 50 ? 86 100101100 300 150 75 ? 51 ? 86
amis ? 30543 http://onsemi.com 20 table 9. circular translator table (continued) msp[8:0] % of imax sm[2:0] msp[8:0] % of imax xxx xxx 100 011 010 001 000 xxx xxx msp[8:0] % of imax esm[2:0] msp[8:0] % of imax 100 011 000 000 000 000 000 010 001 msp[8:0] coil y coil x comp full 1ph comp full 2ph comp 1/2 1/4 1/8 1/16 1/32 1/64 1/128 100101101 301 ? 52 ? 85 100101110 302 151 ? 53 ? 84 100101111 303 ? 55 ? 84 100110000 304 152 76 38 19 ? 56 ? 83 100110001 305 ? 57 ? 82 100110010 306 153 ? 58 ? 82 100110011 307 ? 59 ? 81 100110100 308 154 77 ? 60 ? 80 100110101 309 ? 61 ? 80 100110110 310 155 ? 62 ? 79 100110111 311 ? 62 ? 78 100111000 312 156 78 39 ? 63 ? 77 100111001 313 ? 64 ? 77 100111010 314 157 ? 65 ? 76 100111011 315 ? 66 ? 75 100111100 316 158 79 ? 67 ? 74 100111101 317 ? 68 ? 73 1001 11110 318 159 ? 69 ? 72 1001 11111 319 ? 70 ? 72 101000000 320 160 80 40 20 10 5 2 ? 71 ? 71 101000001 321 ? 72 ? 70 101000010 322 161 ? 72 ? 69 101000011 323 ? 73 ? 68 101000100 324 162 81 ? 74 ? 67 101000101 325 ? 75 ? 66 101000110 326 163 ? 76 ? 65 101000111 327 ? 77 ? 64 101001000 328 164 82 41 ? 77 ? 63 101001001 329 ? 78 ? 62 101001010 330 165 ? 79 ? 62 101001011 331 ? 80 ? 61 101001100 332 166 83 ? 80 ? 60 101001101 333 ? 81 ? 59 101001110 334 167 ? 82 ? 58 101001111 335 ? 82 ? 57 101010000 336 168 84 42 21 ? 83 ? 56 101010001 337 ? 84 ? 55 101010010 338 169 ? 84 ? 53 101010011 339 ? 85 ? 52 101010100 340 170 85 ? 86 ? 51 101010101 341 ? 86 ? 50 101010110 342 171 ? 87 ? 49 101010111 343 ? 88 ? 48
amis ? 30543 http://onsemi.com 21 table 9. circular translator table (continued) msp[8:0] % of imax sm[2:0] msp[8:0] % of imax xxx xxx 100 011 010 001 000 xxx xxx msp[8:0] % of imax esm[2:0] msp[8:0] % of imax 100 011 000 000 000 000 000 010 001 msp[8:0] coil y coil x comp full 1ph comp full 2ph comp 1/2 1/4 1/8 1/16 1/32 1/64 1/128 101011000 344 172 86 43 ? 88 ? 47 101011001 345 ? 89 ? 46 101011010 346 173 ? 89 ? 45 101011011 347 ? 90 ? 44 101011100 348 174 87 ? 90 ? 43 101011101 349 ? 91 ? 42 101011110 350 175 ? 91 ? 41 10101 1111 351 ? 92 ? 39 101100000 352 176 88 44 22 11 ? 92 ? 38 101100001 353 ? 93 ? 37 101100010 354 177 ? 93 ? 36 101100011 355 ? 94 ? 35 101100100 356 178 89 ? 94 ? 34 101100101 357 ? 95 ? 33 101100110 358 179 ? 95 ? 31 101100111 359 ? 95 ? 30 101101000 360 180 90 45 ? 96 ? 29 101101001 361 ? 96 ? 28 101101010 362 181 ? 96 ? 27 101101011 363 ? 97 ? 25 101101100 364 182 91 ? 97 ? 24 101101101 365 ? 97 ? 23 101101110 366 183 ? 98 ? 22 101101111 367 ? 98 ? 21 101110000 368 184 92 46 23 ? 98 ? 20 101110001 369 ? 98 ? 18 101110010 370 185 ? 99 ? 17 101110011 371 ? 99 ? 16 101110100 372 186 93 ? 99 ? 15 101110101 373 ? 99 ? 13 101110110 374 187 ? 99 ? 12 101110111 375 ? 99 ? 11 101111000 376 188 94 47 ? 100 ? 10 101111001 377 ? 100 ? 9 101111010 378 189 ? 100 ? 7 101111011 379 ? 100 ? 6 101111100 380 190 95 ? 100 ? 5 101111101 381 ? 100 ? 4 101111110 382 191 ? 100 ? 2 101111111 383 ? 100 ? 1 110000000 384 192 96 48 24 12 6 3 ? 100 0 110000001 385 ? 100 1 110000010 386 193 ? 100 2
amis ? 30543 http://onsemi.com 22 table 9. circular translator table (continued) msp[8:0] % of imax sm[2:0] msp[8:0] % of imax xxx xxx 100 011 010 001 000 xxx xxx msp[8:0] % of imax esm[2:0] msp[8:0] % of imax 100 011 000 000 000 000 000 010 001 msp[8:0] coil y coil x comp full 1ph comp full 2ph comp 1/2 1/4 1/8 1/16 1/32 1/64 1/128 110000011 387 ? 100 4 110000100 388 194 97 ? 100 5 110000101 389 ? 100 6 110000110 390 195 ? 100 7 110000111 391 ? 100 9 110001000 392 196 98 49 ? 100 10 110001001 393 ? 99 11 110001010 394 197 ? 99 12 110001011 395 ? 99 13 110001100 396 198 99 ? 99 15 110001101 397 ? 99 16 110001110 398 199 ? 99 17 110001111 399 ? 98 18 110010000 400 200 100 50 25 ? 98 20 110010001 401 ? 98 21 110010010 402 201 ? 98 22 110010011 403 ? 97 23 110010100 404 202 101 ? 97 24 110010101 405 ? 97 25 110010110 406 203 ? 96 27 110010111 407 ? 96 28 110011000 408 204 102 51 ? 96 29 110011001 409 ? 95 30 110011010 410 205 ? 95 31 110011011 411 ? 95 33 110011100 412 206 103 ? 94 34 110011101 413 ? 94 35 110011110 414 207 ? 93 36 11001 1111 415 ? 93 37 110100000 416 208 104 52 26 13 ? 92 38 110100001 417 ? 92 39 110100010 418 209 ? 91 41 110100011 419 ? 91 42 110100100 420 210 105 ? 90 43 110100101 421 ? 90 44 110100110 422 211 ? 89 45 110100111 423 ? 89 46 110101000 424 212 106 53 ? 88 47 110101001 425 ? 88 48 110101010 426 213 ? 87 49 110101011 427 ? 86 50 110101100 428 214 107 ? 86 51 110101101 429 ? 85 52
amis ? 30543 http://onsemi.com 23 table 9. circular translator table (continued) msp[8:0] % of imax sm[2:0] msp[8:0] % of imax xxx xxx 100 011 010 001 000 xxx xxx msp[8:0] % of imax esm[2:0] msp[8:0] % of imax 100 011 000 000 000 000 000 010 001 msp[8:0] coil y coil x comp full 1ph comp full 2ph comp 1/2 1/4 1/8 1/16 1/32 1/64 1/128 110101110 430 215 ? 84 53 110101111 431 ? 84 55 110110000 432 216 108 54 27 ? 83 56 110110001 433 ? 82 57 110110010 434 217 ? 82 58 110110011 435 ? 81 59 110110100 436 218 109 ? 80 60 110110101 437 ? 80 61 110110110 438 219 ? 79 62 110110111 439 ? 78 62 110111000 440 220 110 55 ? 77 63 110111001 441 ? 77 64 110111010 442 221 ? 76 65 110111011 443 ? 75 66 110111100 444 222 111 ? 74 67 110111101 445 ? 73 68 110111110 446 223 ? 72 69 110111111 447 ? 72 70 111000000 448 224 112 56 28 14 7 3 ? 71 71 111000001 449 ? 70 72 111000010 450 225 ? 69 72 111000011 451 ? 68 73 111000100 452 226 113 ? 67 74 111000101 453 ? 66 75 111000110 454 227 ? 65 76 111000111 455 ? 64 77 111001000 456 228 114 57 ? 63 77 111001001 457 ? 62 78 111001010 458 229 ? 62 79 111001011 459 ? 61 80 111001100 460 230 115 ? 60 80 111001101 461 ? 59 81 111001110 462 231 ? 58 82 111001111 463 ? 57 82 111010000 464 232 116 58 29 ? 56 83 111010001 465 ? 55 84 111010010 466 233 ? 53 84 111010011 467 ? 52 85 111010100 468 234 117 ? 51 86 111010101 469 ? 50 86 111010110 470 235 ? 49 87 111010111 471 ? 48 88 111011000 472 236 118 59 ? 47 88
amis ? 30543 http://onsemi.com 24 table 9. circular translator table (continued) msp[8:0] % of imax sm[2:0] msp[8:0] % of imax xxx xxx 100 011 010 001 000 xxx xxx msp[8:0] % of imax esm[2:0] msp[8:0] % of imax 100 011 000 000 000 000 000 010 001 msp[8:0] coil y coil x comp full 1ph comp full 2ph comp 1/2 1/4 1/8 1/16 1/32 1/64 1/128 111011001 473 ? 46 89 111011010 474 237 ? 45 89 111011011 475 ? 44 90 111011100 476 238 119 ? 43 90 111011101 477 ? 42 91 111011110 478 239 ? 41 91 111011111 479 ? 39 92 111100000 480 240 120 60 30 15 ? 38 92 111100001 481 ? 37 93 111100010 482 241 ? 36 93 111100011 483 ? 35 94 111100100 484 242 121 ? 34 94 111100101 485 ? 33 95 111100110 486 243 ? 31 95 111100111 487 ? 30 95 111101000 488 244 122 61 ? 29 96 111101001 489 ? 28 96 111101010 490 245 ? 27 96 111101011 491 ? 25 97 111101100 492 246 123 ? 24 97 111101101 493 ? 23 97 111101110 494 247 ? 22 98 111101111 495 ? 21 98 1111 10000 496 248 124 62 31 ? 20 98 1111 10001 497 ? 18 98 1111 10010 498 249 ? 17 99 1111 10011 499 ? 16 99 1111 10100 500 250 125 ? 15 99 1111 10101 501 ? 13 99 111110110 502 251 ? 12 99 111110111 503 ? 11 99 11111 1000 504 252 126 63 ? 10 100 11111 1001 505 ? 9 100 11111 1010 506 253 ? 7 100 111111011 507 ? 6 100 111111100 508 254 127 ? 5 100 111111101 509 ? 4 100 111111110 510 255 ? 2 100 111111111 511 ? 1 100
amis ? 30543 http://onsemi.com 25 figure 10. translator table: circular and square i y i x start = 0 step 1 step 2 step 3 1/4 th micro step i y i x start = 0 step 1 step 2 step 3 uncompensated half step i y i x start = 0 step 1 step 2 compensated half step step 3 i y i x start = 0 step 1 uncompensated full step step 2 step 3 i y i x start = 0 step 1 compensated full step, 1 phase on step 2 step 3 i y i x start = 0 step 1 compensated full step, 2 phase on step 2 step 3 direction the direction of rotation is selected by means of following combination of the dir input pin and the spi ? controlled direction bit . (see table 12 spi control parameter overview) nxt input changes on the nxt input will move the motor current one step up/down in the translator table (even when the motor is disabled: = 0 ). depending on the nxt ? polarity bit (see table 12 spi control parameter overview), the next step is initiated either on the rising edge or the falling edge of the nxt input. translator position the translator position msp[8:0] can be read in spi status register 3 and status register 4 (see table 14 sr3 and sr4). this is a 9 ? bit number equivalent to the 1/128 th micro ? step (see table 9 ?circular translator table?). the translator position is updated immediately following a nxt trigger. nxt update translator position update translator position figure 11. translator position timing diagram synchronization of step mode and nxt input when step mode is re ? programmed to another resolution (figure 12), then this is put in effect immediately upon the first arriving ?nxt? input. if the micro ? stepping resolution is increased, the coil currents will be regulated to the nearest micro ? step, according to the fixed grid of the increased resolution. if however the micro ? stepping resolution is decreased, then it is possible to introduce an offset (or phase shift) in the micro ? step translator table. if the step resolution is decreased at a translator table position that is shared both by the old and new resolution setting, then the offset is zero and micro ? stepping is proceeds according to the translator table. if the translator position is not shared both by the old and new resolution setting, then the micro ? stepping proceeds with an offset relative to the translator table (see figure 12 right hand side).
amis ? 30543 http://onsemi.com 26 ix dir iy ix iy dir nxt1 nxt2 nxt3 nxt4 halfstep endpos 1/4 th step change from lower to higher resolution startpos pc20070604.6 iy ix iy ix dir nxt1 nxt2 nxt3 dir endpos halfstep 1/8 th step change from higher to lower resolution startpos figure 12. nxt ? step mode synchronization left : change from lower to higher resolution. the left ? hand side depicts the ending half ? step position during which a new step mode resolution was programmed. the right ? hand side diagram shows the effect of subsequent nxt commands on the micro ? step position. righ t: change from higher to lower resolution. the left ? hand side depicts the ending micro ? step position during which a new step mode resolution was programmed. the right ? hand side diagram shows the effect of subsequent nxt commands on the half ? step position. note : it is advised to reduce the micro ? stepping resolution only at micro ? step positions that overlap with desired micro ? step positions of the new resolution. programmable peak ? current the amplitude of the current waveform in the motor coils (coil peak current = i max ) is adjusted by means of an spi parameter ?cur[4:0]? (see t able 12 spi control parameter overview). whenever this parameter is changed, the coil ? currents will be updated immediately at the next pwm period. figure 13 presents the peak ? current and current ratings in conjunction to the current setting cur[4:0]. 2 9 15 25 0 cur[4:0] peak current current range 0 cur[4:0] = 0 ? > 2 current range 1 cur[4:0] = 3 ? > 9 current range 2 cur[4:0] = 10 ? > 15 current range 3 cur[4:0] = 16 ? > 25 3090 ma figure 13. programmable peak ? current overview 1205 ma 680 ma 305 ma
amis ? 30543 http://onsemi.com 27 speed and load angle output the sla ? pin provides an output voltage that indicates the level of the back ? e.m.f. voltage of the motor. this back ? e.m.f. voltage is sampled during every so ? called ?coil current zero crossings?. per coil, two zero ? current positions exist per electrical period, yielding in total four zero ? current observation points per electrical period. v bemf zoom t v bb v coil voltage transient next micro ? step previous micro ? step coil current zero crossing current decay zero current t t i coil i coil |v bemf | figure 14. principle of bemf measurement because of the relatively high recirculation currents in the coil during current decay, the coil voltage v coil shows a transient behavior. as this transient is not always desired in application software, two operating modes can be selected by means of the bit (see ?sla ? transparency? in table 12 spi control parameter overview). the sla pin shows in ?transparent mode? full visibility of the voltage transient behavior. this allows a sanity ? check of the speed ? setting versus motor operation and characteristics and supply voltage levels. if the bit ?slat? is cleared, then only the voltage samples at the end of each coil current zero crossing are visible on the sla ? pin. because the transient behavior of the coil voltage is not visible anymore, this mode generates smoother back e.m.f. input for post ? processing, e.g. by software. in order to bring the sampled back e.m.f. to a descent output level (0 v to 5 v), the sampled coil voltage v coil is divided by 2 or by 4. this divider is set through an spi bit . (see table 12 spi control parameter overview) the following drawing illustrates the operation of the sla ? pin and the transparency ? bit. ?pwmsh? and ?i coil = 0? are internal signals that define together with slat the sampling and hold moments of the coil voltage.
amis ? 30543 http://onsemi.com 28 pwmsh icoil=0 slat sla ? pin last sample is retained retain last sample previous output is kept at sla pin buf ssh sh ch csh slat not(icoil=0) icoil=0 pwmsh sla ? pin v coil div2 div4 v bemf t t v coil figure 15. timing diagram of sla ? pin slat = 1 => sla ? pin is ?transparent? during v bemf sampling @ coil current zero crossing. sla ? pin is updated ?real ? time?. slat = 0 => sla ? pin is not ?transparent? during v bemf sampling @ coil current zero crossing. sla ? pin is updated when leaving current ? less state. warning, error detection and diagnostics feedback thermal warning and shutdown when junction temperature rises above t tw , the thermal warning bit is set (table 14 spi status registers address sr0). if junction temperature increases above thermal shutdown level, then the circuit goes in ?thermal shutdown? mode ( ) and all driver transistors are disabled (high impedance) (see t able 14 spi status registers address sr2). the conditions to reset flag is to be at a temperature lower than t tw and to clear the < tsd> flag by reading it using any spi read command. overcurrent detection the overcurrent detection circuit monitors the load current in each activated output stage. if the load current exceeds the over ? current detection threshold, then the overcurrent flag is set and the drivers are switched off to reduce the power dissipation and to protect the integrated circuit. each driver transistor has an individual detection bit (see table 14 spi status registers address sr1 and sr2: and ). error condition is latched and the microcontroller needs to clean the status bits to reactivate the drivers. note : successive reading the spi status registers 1 and 2 in case of a short circuit condition, may lead to damage to the drivers. open coil/current not reached detection open coil detection is based on the observation of 100% duty cycle of the pwm regulator. if in a coil 100% duty cycle is detected for longer than 200 ms then the related driver transistors are disabled (high ? impedance) and an appropriate bit in the spi status register is set ( or ). (table 14) when the resistance of a motor coil is very large and the supply voltage is low , it can happen that the motor driver is not able to deliver the requested current to the motor. under these conditions the pwm controller duty cycle will be 100% and after 200 ms the error pin and , will flag this situation (motor current is kept alive). this feature can be used to test if the operating conditions (supply voltage, motor coil resistance) still allow reaching the requested coil ? current or else the coil current should be reduced. charge pump failure the charge pump is an important circuit that guarantees low r ds(on) for all drivers, especially for low supply voltages. if supply voltage is too low or external components are not properly connected to guarantee r ds(on) of the drivers, then the bit is set (t able 14). also after por the charge pump voltage will need some time to exceed the required threshold. during that time will be set to ?1?.
amis ? 30543 http://onsemi.com 29 error output this is a digital output to flag a problem to the external microcontroller. the signal on this output is active low and the logic combination of: not(errb) = or or or or or logic supply regulator amis ? 30543 has an on ? chip 5 v low ? drop regulator with external capacitor to supply the digital part of the chip, some low ? voltage analog blocks and external circuitry. the voltage level is derived from an internal bandgap reference. to calculate the available drive ? current for external circuitry, the specified i load should be reduced with the consumption of internal circuitry (unloaded outputs) and the loads connected to logic outputs. see table 4. dc parameters power ? on reset (por) function the open drain output pin por /wd provides an ?active low? reset for external purposes. at powerup of amis ? 30543, this pin will be kept low for some time to reset for example an external microcontroller. a small analogue filter avoids resetting due to spikes or noise on the v dd supply. t pu t por t rf vbb v ddh vdd v ddl t pd bit (table 11: spi control registers). once this bit has been set to ?1? (watchdog enable), the microcontroller needs to re ? write this bit to clear an internal timer before the watchdog timeout interval expires. in case the timer is activated and wden is acknowledged too early (before t wdpr ) or not within the interval (after t wdto ), then a reset of the microcontroller will occur through por /wd pin. in addition, a warm/cold boot bit is available (see tables 14 and 15) for further processing when the external microcontroller is alive again. clr pin (=hard reset) logic 0 on clr pin allows normal operation of the chip. to reset the complete digital inside amis ? 30543, the input clr needs to be pulled to logic 1 during minimum time given by t clr (table 5 ac parameters). this reset function clears all internal registers without the need of a power ? cycle, except in sleep mode. logic 0 on clr pin resumes normal operation again. the voltage regulator and charge pump remains functional during and after the reset and the por /wd pin is not activated. watchdog function is reset completely. sleep mode the bit in spi control register 2 (see table 10) is provided to enter a so ? called ?sleep mode?. this mode allows reduction of current ? consumption when the motor is not in operation. the effect of sleep mode is as follows: ? the drivers are put in hiz ? all analog circuits are disabled and in low ? power mode ? all internal registers are maintaining their logic content ? nxt and dir inputs are forbidden ? spi communication remains possible (slight current increase during spi communication) ? oscillator and digital clocks are silent, except during spi communication ? registers cannot be cleared by using the clr pin vbb should be minimum 9 v to be able to enter sleep mode.
amis ? 30543 http://onsemi.com 30 the voltage regulator remains active but with reduced current ? output capability (i loadslp ). the watchdog timer stops running and it?s value is kept in the counter. upon leaving sleep mode, this timer continues from the value it had before entering sleep mode. normal operation is resumed after writing logic ?0? to bit . a startup time is needed for the charge pump to stabilize. after this time, nxt commands can be issued. t pu por/wd pin t por vbb v ddh vdd t t t dspi enable wd acknowledge wd wd timer t por t wdrd = t wdpr or = t wdto >t wdpr and < t wdto t t t wdto figure 17. watchdog timing diagram note: t dspi is the time needed by the external microcontroller to shift ? in the bit after a powerup. the duration of the watchdog timeout interval is programmable through the wdt[3:0] bits (see also table 11: spi control registers. the timing is given in table 10 below. table 10. watchdog timeout interval as function of wdt[3.0] index wdt[3:0] t wdto (ms) index wdt[3:0] t wdto (ms) 0 0000 32 8 1000 288 1 0001 64 9 1001 320 2 0010 96 10 1010 352 3 0011 128 11 1011 384 4 0100 160 12 1100 416 5 0101 192 13 1101 448 6 0110 224 14 1110 480 7 0111 256 15 1111 512
amis ? 30543 http://onsemi.com 31 spi interface the serial peripheral interface (spi) allows an external microcontroller (master) to communicate with amis ? 30543. the implemented spi block is designed to interface directly with numerous micro ? controllers from several manufacturers. amis ? 30543 acts always as a slave and can?t initiate any transmission. the operation of the device is configured and controlled by means of spi registers which are observable for read and/or write from the master. spi transfer format and pin signals during a spi transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). a serial clock line (clk) synchronizes shifting and sampling of the information on the two serial data lines (do and di). do signal is the output from the slave (amis ? 30543), and di signal is the output from the master. a chip select line (cs ) allows individual selection of a slave spi device in a multiple ? slave system. the cs line is active low. if amis ? 30543 is not selected, do is pulled up with the external pull up resistor. since amis ? 30543 operates as a slave in mode 0 (cpol = 0; cpha = 0) it always clocks data out on the falling edge and samples data in on rising edge of clock. the master spi port must be configured in mode 0 too, to match this operation. the spi clock idles low between the transferred bytes. the diagram below is both a master and a slave timing diagram since clk, do and di pins are directly connected between the master and the slave. di msb clk 1 2 3 4 5 6 7 8 cs do # clk cycle msb lsb lsb 6 543 21 6 543 21 figure 18. timing diagram of a spi transfer note: at the falling edge of the eight clock pulse the data ? out shift register is updated with the content of the addressed internal spi register. the internal spi registers are updated at the first rising edge of the amis ? 30543 system clock when cs = high transfer packet: serial data transfer is assumed to follow msb first rule. the transfer packet contains one or more bytes. lsb data command and spi register address cmd2 cmd1 cmd0 addr4 addr3 addr2 addr1 addr0 d7 d6 d5 d4 d3 d2 d1 d0 msb lsb msb byte 1 byte 2 command spi register address figure 19. spi transfer packet byte 1 contains the command and the spi register address and indicates to amis ? 30543 the chosen type of operation and addressed register. byte 2 contains data, or sent from the master in a write operation, or received from amis ? 30543 in a read operation.
amis ? 30543 http://onsemi.com 32 two command types can be distinguished in the communication between master and amis ? 30543: ? read from spi register with address addr[4:0]: cmd2 = ?0? ? write to spi register with address addr[4:0]: cmd2 = ?1? read operation if the master wants to read data from status or control registers, it initiates the communication by sending a read command. this read command contains the address of the spi register to be read out. at the falling edge of the eight clock pulse the data ? out shift register is updated with the content of the corresponding internal spi register. in the next 8 ? bit clock pulse train this data is shifted out via do pin. at the same time the data shifted in from di (master) should be interpreted as the following successive command or dummy data. cs do data from addr1 old data or not valid data data data from previous command or not valid after por or reset di read data from addr 1 command or dummy command figure 20. single read operation where data from spi register with address 1 is read by the master registers are updated with internal status at the rising edge of the internal amis ? 30543 clock when cs = 1 all 4 status registers (see spi registers) contain 7 data bits and a parity check bit. the most significant bit (d7) represents a parity of d[6:0]. if the number of logical ones in d[6:0] is odd, the parity bit d7 equals ?1?. if the number of logical ones in d[6:0] is even then the parity bit d7 equals ?0?. this simple mechanism protects against noise and increases the consistency of the transmitted data. if a parity check error occurs it is recommended to initiate an additional read command to obtain the status again. also the control registers can be read out following the same routine. control registers don?t have a parity check. the cs line is active low and may remain low between successive read commands as illustrated in figure 22. there is however one exception. in case an error condition is latched in one of status registers (see spi registers) the err pin is activated (see section error output). this signal flags a problem to the external microcontroller. by reading the status registers information about the root cause of the problem can be determined. after this read operation the status registers are cleared. because the status registers and err pin (see spi registers) are only updated by the internal system clock when the cs line is high, the master should force cs high immediately after the read operation. for the same reason it is recommended to keep the cs line high always when the spi bus is idle. write operation if the master wants to write data to a control register it initiates the communication by sending a write command. this contains the address of the spi register to write to. the command is followed with a data byte. this incoming data will be stored in the corresponding control register after cs goes from low to high! amis ? 30543 responds on every incoming byte by shifting out via do the data stored in the last received address. it is important that the writing action (command ? address and data) to the control register is exactly 16 bits long. if more or less bits are transmitted the complete transfer packet is ignored. a write command executed for a read ? only register (e.g. status registers) will not affect the addressed register and the device operation. because after a power ? on ? reset the initial address is unknown the data shifted out via do is not valid.
amis ? 30543 http://onsemi.com 33 di cs do write data to addr3 new data for addr3 old data from addr3 old data or not valid command data data data from previous command or not valid after por or reset data figure 21. single write operation where data from the master is written in spi register with address 3 the new data is written into the corresponding internal register at the rising edge of cs examples of combined read and write operations in the following examples successive read and write operations are combined. in figure 22 the master first reads the status from register at addr4 and at addr5 followed by writing a control byte in control register at addr2. note that during the write command the old data of the pointed register is returned at the moment the new data is shifted in di cs do read data from addr4 old data or not valid command data data data from previous command or not valid after por or reset command command data data data data from addr4 read data from addr5 data from addr5 write data to addr 2 new data for addr2 old data from addr2 figure 22. 2 successive read commands followed by a write command registers are updated with the internal status at the rising edge of the internal amis ? 30543 clock when cs = 1 the new data is written into the corresponding internal register at the rising edge of cs after the write operation the master could initiate a read back command in order to verify the data correctly written as illustrated in figure 23. during reception of the read command the old data is returned for a second time. only after receiving the read command the new data is transmitted. this rule also applies when the master device wants to initiate an spi transfer to read the status registers. because the internal system clock updates the status registers only when cs line is high, the first read out byte might represent old status information.
amis ? 30543 http://onsemi.com 34 di cs do write data to addr2 old data or not valid command data data data from previous command or not valid after por or reset command data data data old data from addr2 new data for addr2 old data from addr2 read data from addr2 command or dummy new data from addr2 figure 23. a write operation where data from the master is written in spi register with address 2 followed by a read back operation to confirm a correct write operation registers are updated with the internal status at the rising edge of cs the new data is written into the corresponding internal register at the rising edge of cs note: the internal data ? out shift buffer of amis ? 30543 is updated with the content of the selected spi register only at the last (every eight) falling edge of the clk signal (see spi transfer format and pin signals). as a result, new data for transmission cannot be written to the shift buffer at the beginning of the transfer packet and the first byte shifted out might represent old data. table 11. spi control registers (all spi control registers have read/write access and default to ?0? after power ? on or hard reset) address content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 wr (00h) data wden wdt[3:0] ? ? ? cr0 (01h) data sm[2:0] cur[4:0] cr1 (02h) data dirctrl nxtp ? ? pwmf pwmj emc[1:0] cr2 (03h) data moten slp slag slat ? ? ? ? cr3 (09h) data ? ? ? ? ? esm[2:0] where : r/w read and write access reset: status after power ? on or hard reset
amis ? 30543 http://onsemi.com 35 table 12. spi control parameter overview symbol description status value dirctrl controls the direction of rotation (in combination with logic level on input dir) = 0 = 0 cw motion (note 15) = 1 ccw motion (note 15) = 1 = 0 ccw motion (note 15) = 1 cw motion (note 15) nxtp selects if nxt triggers on rising or falling edge = 0 trigger on rising edge = 1 trigger on falling edge emc[1:0] turn on ? turn ? off slopes of motor driver (note 14) 00 very fast 01 fast 10 slow 11 very slow slat speed load angle transparency bit = 0 sla is not transparent = 1 sla is transparent slag speed load angle gain setting = 0 gain = 0.5 = 1 gain = 0.25 pwmf enables doubling of the pwm frequency (note 14) = 0 default frequency = 1 double frequency pwmj enables jittery pwm = 0 jitter disabled = 1 jitter enabled sm[2:0] stepmode (only valid if esm[2:0] = 000) 000 1/32 micro ? step 001 1/16 micro ? step 010 1/8 micro ? step 011 1/4 micro ? step 100 compensated half step 101 uncompensated half step 110 uncompensated full step 111 uncompensated full step esm[2:0] stepmode 001 1/128 micro ? step 010 1/64 micro ? step 011 compensated full step, 2 phase on 100 compensated full step, 1 phase on other stepping mode defined by sm[2:0] slp enables sleep mode (if v bb > 9 v) = 0 active mode = 1 sleep mode moten activates the motor driver outputs = 0 drivers disabled = 1 drivers enabled 14. the typical values can be found in table 4: dc parameters and in table 5: ac parameters 15. depending on the wiring of the motor connections
amis ? 30543 http://onsemi.com 36 cur[4:0] selects imcmax peak. this is the peak or amplitude of the regulated current waveform in the motor coils. table 13. spi control parameter overview cur[4:0] current range (note 17) index cur[4:0] current (ma) (note 16) current range (note 17) index cur[4:0] current (ma) (note 16) 0 0 00000 132 3 16 10000 1405 1 00001 245 17 10001 1520 2 00010 355 18 10010 1695 1 3 00011 395 19 10011 1850 4 00100 445 20 10100 2070 5 00101 485 21 10101 2240 6 00110 540 22 10110 2440 7 00111 585 23 10111 2700 8 01000 640 24 11000 2845 9 01001 715 25 11001 3000 2 10 01010 780 26 11010 3000 11 01011 870 27 11011 3000 12 01100 955 28 11100 3000 13 01101 1060 29 11101 3000 14 01110 1150 30 11110 3000 15 01111 1260 31 11111 3000 16. typical current amplitude at t j = 125 17. reducing the current over different current ranges might trigger overcurrent detection. see dedicated application note for s olutions spi status register description all 4 spi status registers have read access and are default to ?0? after power ? on or hard reset. table 14. spi status registers address content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access r r r r r r r r reset 0 0 0 0 0 0 0 0 sr0 (04h) data is not latched par tw cpfail wd opencoil_x opencoil_y sr1 (05h) data is latched par ovcxpt ovcxpb ovcxnt ovcxnb ? ? ? sr2 (06h) data is latched par ovcypt ovcypb ovcynt ovcynb tsd ? ? sr3 (07h) data is not latched par msp[8:2] sr4 (0ah) data is not latched par msp[6:0] where : r read only mode access reset status after power ? on or hard reset par parity check
amis ? 30543 http://onsemi.com 37 table 15. spi status flags overview mnemonic flag length (bit) related spi register comment reset state cpfail charge pump failure 1 status register 0 ?0? = no failure ?1? = failure: indicates that the charge pump does not reach the required voltage level. note 1 ?0? msp[8:0] micro ? step position 9 status register 3 and status register 4 translator micro step position ?000000000? openx open coil x 1 status register 0 ?1? = open coil detected ?0? openy open coil y 1 status register 0 ?1? = open coil detected ?0? ovcxnb ov er c urrent on x h ? bridge; mot xn terminal; b ottom tran. 1 status register 1 ?0? = no failure ?1? = failure: indicates that over current is detected at bottom transistor xn ? terminal ?0? ovcxnt ov er c urrent on x h ? bridge; mot xn terminal; t op transist. 1 status register 1 ?0? = no failure ?1? = failure: indicates that over current is detected at top transistor xn ? terminal ?0? ovcxpb ov er c urrent on x h ? bridge; mot xp terminal; b ottom tran. 1 status register 1 ?0? = no failure ?1? = failure: indicates that over current is detected at bottom transistor xp ? terminal ?0? ovcxpt ov er c urrent on x h ? bridge; mot xp terminal; t op transist. 1 status register 1 ?0? = no failure ?1? = failure: indicates that over current is detected at top transistor xp ? terminal ?0? ovcynb ov er c urrent on y h ? bridge; motyn terminal; b ottom tran. 1 status register 2 ?0? = no failure ?1? = failure: indicates that over current is detected at bottom transistor yn ? terminal ?0? ovcynt ov er current on y h ? bridge; mot yn terminal; t op transist. 1 status register 2 ?0? = no failure ?1? = failure: indicates that over current is detected at top transistor yn ? terminal ?0? ovcypb ov er c urrent on y h ? bridge; mot yp terminal; b ottom tran. 1 status register 2 ?0? = no failure ?1? = failure: indicates that over current is detected at bottom transistor yp ? terminal ?0? ovcypt ov er c urrent on y h ? bridge; mot yp terminal; t op transist. 1 status register 2 ?0? = no failure ?1? = failure: indicates that over current is detected at top transistor yp ? terminal ?0? tsd thermal shutdown 1 status register 2 ?0? tw thermal warning 1 status register 0 ?0? wd watchdog event 1 status register 0 ?1? = watchdog reset after time ? out ?0? note: wd ? this bit indicates that the watchdog timer has not been cleared properly. if the master reads that wd is set to ?1? after rese t, it means that a watchdog reset occurred (warm boot) instead of por (cold boot). wd bit will be cleared only when the master writes ?0? to wden bit. table 16. ordering information part no. peak current temperature range package shipping ? amis30543c5431g 3000 ma ? 40 c to 125 c nqfp ? 32 (7 x 7 mm) (pb ? free) units / tubes amis30543c5431rg 3000 ma ? 40 c to 125 c nqfp ? 32 (7 x 7 mm) (pb ? free) tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
amis ? 30543 http://onsemi.com 38 package dimensions qfn32 case 485j ? 02 issue c note 3 l d2 b 1 9 16 17 32 25 e2 32x 8 24 32x seating plane 0.15 c (a3) a a1 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 2x k 8 4x top view side view bottom view exposed pad pin 1 location 0.15 c 2x e d a b 0.10 c 0.08 c c e 0.10 c 0.05 c a b e dim min nom max millimeters a 0.800 0.900 1.000 a1 0.000 0.025 0.050 a3 0.200 ref b 0.250 0.250 0.350 d 7.00 bsc d2 5.160 5.260 5.360 e 7.00 bsc e2 5.160 5.260 5.360 e 0.650 bsc k 0.200 ??? ??? l 0.300 0.400 0.500 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 amis ? 30543/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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